In any data processing system in which there are separate functional units each controlled by its own internal clocks and connected together via asynchronous interfaces, there exists the requirement that any two units must be synchronized before communication can take place on their mutual interface.
Also, when designing logic circuits it is desirable to have all signal changes synchronized to the same clocking system. This helps to avoid circuit race conditions and latch metastability problems. Where signals are received asynchronously from other systems a synchronizing circuit must be used to achieve this.
Signals feeding clocked, synchronous logic that are not synchronized with those clocks can produce erroneous results. Since such signals can change at any time within a clock cycle, the data setup and hold time specifications on the latches can be violated, thus causing oscillations or "metastability" to occur in the latches or detection of the signal to be missed. (Metastability is the condition where a latch is changing its state when the clock is turned "off", but is neither a 1 nor a 0. This condition can persist for a long period of time, depending upon the technology and latch design). All latches have data setup and hold time specifications, so this problem occurs in any clocked logic design.
The drawbacks of some of the simpler methods of using a pair of latches, each set by two separated clocks, to synchronize an input signal with the second latch clock are discussed in an article entitled "High Speed Synchronization Cicuitry" by G. Doettling et al (IBM Technical Disclosure Bulletin, Vol 30, No 9, Feb. 1988 pp 236-241). A more complex arrangement is proposed to provide synchronization with the minimum delay. This involves the use of four separate clocks and six latches and although delay is reduced, the circuit is only semi-synchronized as the output may be synchronized to either one of a pair of clocks. The circtuit is designed to synchronize "tags" where the duration of the signal to be synchronized is greater than one clock cycle.
European patent application, EPA 0141946 A2 discusses the problem of synchronizing shorter signal pulses with clock pulses where there is jitter on the incoming signal. The circuit described in the EPA, employs a delay element and applies incoming pulses both directly and after a delay to respective latches which are clocked by a clock derived from the system clock. The output of the two latches is compared and, if different indicates jitter relative to the active clock edge. If jitter is indicated, an Exclusive-Or gate to which the system clock is applied acts to modify the derived clock signal. This operates the latches such that the output of a third latch which is clocked by the system clock and receives the output of the undelayed latch, is brought and receives the output of the undelayed latch, is brought into synchronization with the input signal with no more than one initial erroneous transition.